SynaptiCAD AllProducts v13.09a
TestBencher Pro is a graphical test bench generator that dramatically reduces the time required to create and maintain test benches. One of the most time consuming tasks for users of HDL languages is coding test benches to verify the operation of their design. In his book "Writing Testbenches," Janick Bergeron estimates that 70% of design time is spent verifying HDL code models and that the test bench makes up 80% of the total HDL code generated during product development.
BugHunter uses the SynaptiCAD graphical environment and supports all major HDL simulators. It has the ability to launch the simulator, provide single step debugging, unit-level test bench generation, streaming of waveform data, project management, and a hierarchy tree. The unit-level test bench generation is unique in that it lets the user draw stimulus waveforms and then generates the stimulus model and wrapper code and launches the code. It is one of the fastest ways to test a model and make sure that everything is working correctly. The debugger also has exceptional support for VCD waveform files.
VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx.
WaveFormer Pro is a revolutionary new rapid-prototyping EDA tool that helps you design faster and with fewer mistakes. WaveFormer Pro enables you to automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing and perform Boolean level simulation without the need for schematics or simulation models. When your timing diagram is complete, you can then generate digital stimuli for your favorite Verilog, VHDL, SPICE or gate-level simulator. WaveFormer Pro also has the ability to import and annotate simulation and logic analyzer data, for publication quality design documentation.
DataSheet Pro is SynaptiCAD"s top of the line timing digaram editor, providing the ultimate environment for documentation professionals working with multi-diagram projects. Datasheet Pro"s project management features allow users to efficiently combine diagrams from multiple engineers into one project with uniform formatting. Using Linking and Embedding (OLE), users can embed timing diagrams into other publishing programs. These images can be edited at any time directly from the publishing program by double clicking on the image to launch DataSheet Pro with the selected timing diagram. Other features include style sheets, view support, web-ready image generation, analog waveform import and display, and support for the industry-standard Timing Diagram Markup Language (TDML) format. Documentation professionals will be able to receive timing diagrams produced by design engineers using any TDML-compatible product, such as WaveFormer Pro or Timing Diagrammer Pro, and embed them directly into publishing programs like FrameMaker and Word.
Timing Diagrammer Pro has everything that you expect in a timing diagram editor: a modeless drawing and editing environment; delays, setups, and holds for performing timing analysis; time markers; seven graphical waveform states; virtual and group buses; clocks with formulas; as well as a variety of ways to document your work. A great timing analysis tool at a great price, Timing Diagrammer Pro is a must-have for any engineer.
Designers are often in the situation where they are working in one language, but one model that comes from a vendor or another group in a different language. Translating the model is a quick way to get it into the language that is the most easy for you to simulate and debug in. To meet this translation need SynaptiCAD offers both VHDL and Verilog translation services and the tools for you to do the translation yourself.
Gigawave Viewer combines SynaptiCAD"s
free VCD WaveViewer with our high-performance gigawave compression engine to create the lowest cost waveform viewer capable of handling
multi-gigabyte VCD files. Gigawave viewer also comes with a PLI-based library that can be integrated with your favorite simulator to generate highly compressed BTIM files. Using BTIM waveform dumping can speed up simulation by up to 6x over dumping using an ordinary VCD dump and the resulting files are generally 200x smaller. BTIM files also load much faster than VCD files (typically around 500x faster)! GigaWave also loads SPICE results, TDML, logic analyzer data, and more.
SynaptiCAD"s new Transaction Tracker is a PSL/Sugar-based verification tool for viewing simulation data as higher-level transactions, instead of as simple waveforms. Users specify transaction patterns (temporal assertions) to match against using the PSL Sugar language, and Transaction Tracker displays matches and partial matches of these patterns graphically as "transaction records".
This tool also provides a powerful interface for learning the syntax of the PSL language. Several simulators have been released that support PSL assertions, but one of the problems is that users have to learn another language before they become effective with using the tool. With Transaction Tracker, the results are graphical and instantaneous, so users can build up complicated equations by typing in a few terms and seeing the results and then continually adding on until the code matches to the correct transaction pattern.
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