Libero IDE Platinum SP1
•
Libero IDE Platinum SP1 8.6.2.10
.fullpost{display:inline;}
Libero IDE offers the latest and best-in-class FPGA development tools from leading EDA vendors such as Mentor Graphics and Synplicity. These tools, combined with Actel developed tools allow you to quickly and easily manage your Actel FPGA designs. An intuitive user interface and powerful design manager guides you through the process while organizing design files and seamlessly managing exchanges between the various tools.
Libero IDE Software Features:
Libero Integrated Design Environment (IDE) is Actel"s comprehensive software toolset for designing with all Actel FPGAs.
From design, synthesis and simulation, through floorplanning, place-and-route, timing constraints and analysis, power analysis, and program file generation, Libero IDE manages the entire design flow quickly and efficiently. Libero"s SmartDesign provides an efficient methodology for creating complete simple and complex processor based System on Chip (SoC) designs with ease.
Libero IDE provides full power optimization and analysis tools for Actel"s low-power flash FPGA families, including IGLOO Series, ProASIC3 Series, and Actel Fusion® mixed-signal FPGAs.
Libero IDE offers the latest and best-in-class FPGA development tools from leading EDA vendors such as Mentor Graphics and Synplicity. These tools, combined with Actel developed tools allow you to quickly and easily manage your Actel FPGA designs. An intuitive user interface and powerful design manager guides you through the process while organizing design files and seamlessly managing exchanges between the various tools.
Libero IDE Software Features:
- Powerful project and design flow management
- Full suite of integrated design entry tools and methodologies:
- SmartDesign graphical SoC design creation with automatic abstraction to HDL
- Core Catalog and Configuration
- HDL and HDL templates
- "User-defined block" creation flow for design re-use
- ViewDraw Schematic Capture
- Actel cell libraries
- Synplify/Synplify Pro AE synthesis fully optimizes Actel FPGA device performance and area utilization
- Synplify DSP AE performs high-level DSP optimizations within a Simulink environment
- ModelSim VHDL or Verilog behavioral, post-synthesis and post-layout simulation capability
- Designer physical design implementation, floorplanning, physical constraints, and layout
- Timing- and power-driven place-and-route
- SmartTime environment for timing constraint management and analysis
- SmartPower provides comprehensive power analysis for actual and "what if" power scenarios
- Interface to FlashPro and Silicon Sculptor programming software
- Post-route probe insertion and Identify AE debugging software for Actel flash designs
- Silicon Explorer debugging software for Actel antifuse designs